The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a need of obtaining an adequate interlayer overlay raises challenges to control, relieve and compensate a composite stress built up on a lithograph mask during fabrication of the mask. Several approaches of reducing overlay error have been applied, such as an e-beam correction, a charging dissipation layer deposition, and manipulating blank flatness. Accordingly, although existing approaches have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, variations of pattern density and device layout from area to area in a lithography mask raise need of a stress compensation solution not only globally (a whole mask) but also locally (a portion of the mask). It is desired to have improvements in this area.